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IPC 7
  G06F - G06F 7/72  
G06F00900-G06F01342
  G06F 15/00 - G06F 171:00  

SECTION G – PHYSICS


G 06COMPUTING; CALCULATING; COUNTING (score computers for games A63B 71/06, A63D 15/20, A63F 1/18; combinations of writing implements with computing devices B43K 29/08)


G 06 FELECTRIC DIGITAL DATA PROCESSING (computers in which a part of the computation is effected hydraulically or pneumatically G06D, optically G06E; self-contained input or output peripheral equipment G06K; computer systems based on specific computational models G06N; impedance networks using digital techniques H03H)


9/

00Arrangements for programme control, e.g. control unit (programme control for peripheral devices G06F 13/10) [4]

9/

02.using wired connections, e.g. plugboard

9/

04.using record carriers containing only programme instructions (G06F 9/06 takes precedence)

9/

06.using stored programme, i.e. using internal store of processing equipment to receive and retain programme

9/

22..Micro-control or micro-programme arrangements  [3]

9/

24...Loading of the micro-programme  [3]

9/

26...Address formation of the next micro-instruction (G06F 9/28 takes precedence)  [3]

9/

28...Enhancement of operational speed, e.g. by using several micro-control devices operating in parallel  [3]

9/

30..Arrangements for executing machine- instructions, e.g. instruction decode (for executing micro-instructions G06F 9/22; for executing subprogrammes G06F 9/40)  [3]

9/

302...Controlling the executing of arithmetic operations  [5]

9/

305...Controlling the executing of logical operations  [5]

9/

308...Controlling single bit operations (G06F 9/305 takes precedence)  [5]

9/

312...Controlling loading, storing or clearing operations  [5]

9/

315...Controlling moving, shifting or rotation operations  [5]

9/

318...with operation extension or modification  [5]

9/

32...Address formation of the next instruction, e.g. incrementing the instruction counter, jump (G06F 9/38 takes precedence; subprogramme jump G06F 9/42)  [3]

9/

34...Addressing or accessing the instruction operand or the result (address translation G06F 12/00)  [3,5]

9/

345....of multiple operands or results  [5]

9/

35....Indirect addressing  [5]

9/

355....Indexed addressing  [5]

9/

38...Concurrent instruction execution, e.g. pipeline, look ahead  [3]

9/

40..Arrangements for executing subprogrammes, i.e. combinations of several instructions  [3]

9/

42...Formation of subprogramme-jump address or of return address  [3]

9/

44..Arrangements for executing specific programmes  [3]

9/

445...Programme loading or initiating  [5]

9/

45...Compilation or interpretation of high level programme languages  [5]

9/

455...Emulation; Software simulation  [5]

9/

46..Multiprogramming arrangements  [3]

9/

48...Programme initiating; Programme switching, e.g. by interrupt [7]

 

9/

50...Allocation of resources, e.g. of the central processing unit (CPU) [7]

 

9/

52...Programme synchronisation; Mutual exclusion, e.g. by means of semaphores [7]

 

9/

54...Interprogramme communication [7]

 


11/

00Error detection; Error correction; Monitoring (methods or arrangements for verifying the correctness of marking on a record carrier G06K 5/00; in information storage based on relative movement between record carrier and transducer G11B, e.g. G11B 20/18; in static stores G11C; coding, decoding or code conversion, for error detection or error correction, in general H03M 13/00) [4]

11/

07.Responding to the occurrence of a fault, e.g. fault tolerance [7]

 

11/

08..Error detection or correction by redundancy in data representation, e.g. by using checking codes

11/

10...Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

11/

14..Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result (G06F 11/16 takes precedence)  [3]

11/

16..Error detection or correction of the data by redundancy in hardware  [3]

11/

18...using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits  [3]

11/

20...using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements  [3]

11/

22.Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing (testing of digital circuits, e.g. of separate computer components, G01R 31/317)  [3]

11/

24..Marginal testing  [3]

11/

25..Testing of logic operation, e.g. by logic analysers  [6]

11/

26..Functional testing  [3]

11/

263...Generation of test inputs, e.g. test vectors, patterns or sequences  [6]

11/

267...Reconfiguring circuits for testing, e.g. LSSD, partitioning  [6]

11/

27...Built-in tests  [6]

11/

273...Tester hardware, i.e. output processing circuits  [6]

11/

277....with comparison between actual response and known fault-free response  [6]

11/

28.by checking the correct order of processing (G06F 11/07, G06F 11/22 take precedence; monitoring patterns of pulse trains H03K 5/19)  [3]

11/

30.Monitoring  [3]

11/

32..with visual indication of the functioning of the machine  [3]

11/

34..Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation  [3]

11/

36.Preventing errors by testing or debugging of software [7]

 


12/

00Accessing, addressing or allocating within memory systems or architectures (information storage in general G11) [4,5]

12/

02.Addressing or allocation; Relocation (programme address sequencing G06F 9/00; arrangements for selecting an address in a digital store G11C 8/00)  [4]

12/

04..Addressing variable-length words or parts of words  [4]

12/

06..Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication (G06F 12/08 takes precedence)  [4]

12/

08..in hierarchically structured memory systems, e.g. virtual memory systems  [4]

12/

10...Address translation  [4]

12/

12...Replacement control  [4]

12/

14.Protection against unauthorised use of memory  [4]

12/

16.Protection against loss of memory contents  [4]


13/

00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F 3/00; multi-processor systems G06F 15/16; transmission of digital information in general H04L; selecting H04Q) [4]

13/

10.Programme control for peripheral devices (G06F 13/14 to G06F 13/42 take precedence)  [4]

13/

12..using hardware independent of the central processor, e.g. channel or peripheral processor  [4]

13/

14.Handling requests for interconnection or transfer  [4]

13/

16..for access to memory bus (G06F 13/28 takes precedence)  [4]

13/

18...with priority control  [4]

13/

20..for access to input/output bus  [4]

13/

22...using successive scanning, e.g. polling (G06F 13/24 takes precedence)  [4]

13/

24...using interrupt (G06F 13/32 takes precedence)  [4]

13/

26....with priority control  [4]

13/

28...using burst mode transfer, e.g. direct memory access, cycle steal (G06F 13/32 takes precedence)  [4]

13/

30....with priority control  [4]

13/

32...using combination of interrupt and burst mode transfer  [4]

13/

34....with priority control  [4]

13/

36..for access to common bus or bus system  [4]

13/

362...with centralised access control  [5]

13/

364....using independent requests or grants, e.g. using separated request and grant lines  [5]

13/

366....using a centralised polling arbiter  [5]

13/

368...with decentralised access control  [5]

13/

37....using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing  [5]

13/

372....using a time-dependent priority, e.g. individually loaded time counters or time slot  [5]

13/

374....using a self-select method with individual priority code comparator  [5]

13/

376....using a contention resolving method, e.g. collision detection, collision avoidance  [5]

13/

378....using a parallel poll method  [5]

13/

38.Information transfer, e.g. on bus (G06F 13/14 takes precedence)  [4]

13/

40..Bus structure  [4]

13/

42..Bus transfer protocol, e.g. handshake; Synchronisation (synchronisation in transmission of digital information in general H04L 7/00)  [4]

  G06F - G06F 7/72    G06F 15/00 - G06F 171:00  
 

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